Once a semiconductor design is completed, the design is sent to a photomask vendor. The photomask vendor then generates a job deck that is to be used to fabricate the masks. After a verification process in which the mask manufacturer verifies that the patterns in each mask layer in the job deck accurately represent the patterns in the design, the photomask vendor sends the job deck to the customer. The customer then performs a final verification process prior to authorizing the photomask vendor to fabricate the masks. This final verification process is important to the customer since an undiscovered error could require fabrication of a whole new set of masks. This can be quite expensive since complex semiconductor mask sets often cost several million dollars.
The final verification process is typically preformed by rendering each mask layer to be verified electronically into an image file that can be viewed on a computer and generating a viewable image on the computer that is commonly referred to as a “job deck view.” The engineer performing the verification process visually inspects the job deck view on a computer, moving around in the image file until a particular pattern is found. The pattern is then checked, and the engineer moves on to the next pattern to be checked. When patterns are found that should not be present, when patterns are missing or when patterns have the wrong size or shape a mask data handling error has probably occurred. The error can then be corrected prior to fabrication of photomasks.
Some parts of the final verification process, such as checking mask tone and spacing, are easily performed since the engineer can use an easily located pattern outside of the die region such as, for example, the layer ID. Checking for metal cheesing is also relatively easy since it does not require that any particular metal pattern be visually inspected.
However, checking Boolean generations, dummy metals, feature width and transistor polysilicon sizing is significantly more difficult, time consuming and prone to error since the engineer must individually verify the presence or absence of particular patterns and/or measure individual patterns in the design. Checking Boolean generation is particularly difficult. In the Boolean generation checking process the engineer must go into the die region of the design to check to make sure that all required layers and sub-layers of the design layout are included in the mask layer being verified. In particular, the engineer must move around in the die region of the image file for each mask layer to find patterns that should be present in the particular mask layer. In addition, the engineer may need to go to a location of patterns that should not be present on the particular mask layer to make sure that they are not present. This process is tedious, time consuming and error prone since it is often difficult to find the pattern to be verified among the many other similar patterns.
The time required to find each pattern to be verified increases with the complexity of the design, making it harder and harder to verify individual mask layers as more complex devices are designed. Moreover, photomask costs have significantly increased as designs have become more complex and as feature sizes have decreased, making the cost of a verification error increasingly significant.
In light of the above, a need exists for an improved method and apparatus for detecting mask data handling errors.